1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device having a plurality of I/O terminal groups.
2. Description of the Background Art
Such a conventional dynamic random access memory, which is a kind of semiconductor memory device and will also be referred to as a "DRAM", has been known that I/O terminal groups are divided into a plurality of groups, and data is input/output via these plurality of I/O terminal groups.
FIG. 13 is a block diagram showing a whole structure of a conventional DRAM.
Referring to FIG. 13, a DRAM 103 includes a memory cell array 1, a sense-refresh amplifier and I/O control circuit 11, a row decoder 12, a column decoder 13, an address buffer 14, a clock generating circuit 20, a write control circuit 3, a lower input buffer 4, an upper input buffer 5, an lower output buffer 600, an upper output buffer 700, an address input terminal group 80, a lower I/O terminal group 81, an upper I/O terminal group 82, signal input terminals 83-87, a power supply terminal 88 and a ground terminal 89.
DRAM 103 operates by receiving a power supply potential Vcc from power supply terminal 88 and receiving a ground potential Vss from ground terminal 89. Memory cell array 1 has a plurality of dynamic memory cells (not shown) arranged in rows and columns, and operates to accumulate storage information at the respective memory cells. Address input terminal group 80 has a plurality of address input terminals.
Address buffer 14 externally receives address signals A0-A9 via address input terminal group 80. Address buffer 14 sends received address signals A0-A9 to row decoder 12 as internal address signals, and also sends received address signals A0-A7 to column decoder 4 as internal address signals.
Row decoder 12 is responsive to the applied address signal to designating a row in memory cell array 1. For this designation, a word line (not shown) is selected. Column decoder 13 is responsive to the applied address signal to designate a column in memory cell array 1. For this designation, a bit line pair (not shown) is selected.
In a read operation, data read from the selected memory cell in memory cell array 1 is transmitted to lower data I/O terminal group 81 via sense-refresh amplifier and I/O control circuit 11 and lower output buffer 600. Data read from the memory cell is transmitted to upper data I/O terminal group 82 via sense-refresh amplifier and I/O control circuit 11 and upper output buffer 700. Data DQ1-DQ16 transmitted in this manner are externally output.
In a write operation, data DQ1-DQ8 input via lower data I/O terminal group 81 are written in the selected memory cells in memory cell array 1 via lower input buffer 4 and sense-refresh amplifier and I/O control circuit 11.
Data DQ9-DQ16 input via upper data I/O terminal group 82 are written in the selected memory cells in memory cell array 1 via upper input buffer 5 and sense-refresh amplifier and I/O control circuit 11.
DRAM 103 is controlled in response to a row address strobe signal /RAS externally applied via signal input terminal 83, a column address strobe signal /CAS externally applied via signal input terminal 84, a lower write designating signal /LW externally applied via signal input terminal 85, an upper write designating signal /UW externally applied via signal input terminal 86 and an output enable signal /OE externally applied via signal input terminal 87. In the description, the symbol "/" indicates an inverted signal.
The clock generating circuit 20 receives signals /RAS, /CAS, /LW, /UW and /OE, and generate signals such as a clock signal in response to these signals. The signals generated from clock generating circuit 20 are applied to sense-refresh amplifier and I/O control circuit 11, row decoder 12, column decoder 13, address buffer 14, write control circuit 3, lower output buffer 600 and upper output buffer 700, respectively.
Sense-refresh amplifier and I/O control circuit 11, row decoder 12, column decoder 13 and address buffer 14 are responsive to the signals sent from clock generating circuit 20.
Write control circuit 3 receives signals /LW and /UW as well as signals sent from clock generating circuit 20, lower output buffer 600 and upper output buffer 700. In response to these received signals, write control circuit 3 outputs the signals for controlling lower input buffer 4 and upper input buffer 5.
Each of lower input buffer 4 and upper input buffer 5 is responsive to the signal sent from write control circuit 3. Each of lower and upper output buffers 600 and 700 is responsive to signal /OE and the signals sent from clock generating circuit 20.
An example of an operation mode of the DRAM thus constructed will be described below. First, description will be given on an early write mode. The early write mode is an operation mode in which signal /LW or /UW for designating or instructing the write operation is raised to start the write operation after falling of signal /RAS for externally taking in the row address signal and before falling of signal /CAS for taking in the column address signal.
In order to execute the early write mode, DRAM 103 must has circuits shown in FIGS. 14 and 16 which will be described below.
FIG. 14 is a circuit diagram showing a conventional early write detecting circuit for executing the early write mode.
Referring to FIG. 14, an early write detecting circuit 2000 is included in clock generating circuit 20 in FIG. 13. Early write detecting circuit 2000 includes inverters 231-233, 235-238 and 243-245, NOR gates 239-241 and NAND gates 234 and 242.
Signal /CAS is applied to one of input terminals of NAND gate 234 through inverters 231, 232 and 233. A signal /CAS0 is output from a node between the output terminal of inverter 232 and the input terminal of inverter 233. Signal /CAS0 is an internal signal of signal /CAS.
Signal /RAS is applied to one of input terminals of each of NOR gates 239 and 240 through inverters 235, 236, 237 and 238. A signal /RASC is output from a node near the output terminal of inverter 238. Signal /RASC is an internal signal of signal /RAS.
Signal /LW is applied to the other input terminal of NOR gate 239. Signal /UW is applied to the other input terminal of NOR gate 240. In NOR gate 241, the output signal of NOR gate 239 is applied to one of its input terminals, and the output signal of NOR gate 240 is applied to the other input terminal. The output signal of NOR gate 241 is applied to one of input terminals of NAND gate 242.
The output signal of NAND gate 242 is applied to the other input terminal of NAND gate 234. The output signal of NAND gate 234 is applied to the other input terminal of NAND gate 242 and is also output as an early write detecting signal EW through inverters 243, 244 and 245.
Early write detecting circuit 2000 thus constructed operates in the following manner. When signal /RAS is at the H-level, both the output signals of NOR gates 239 and 240 attain the L-level. In this case, therefore, the output signal of NOR gate 241 attains the H-level.
When signal /RAS is at the L-level, the output signal of NOR gate 239 attains the level equal to the inverted level of signal /LW, and the output signal of NOR gate 240 attains the level equal to the inverted level of signal /UW.
When signal /RAS is at the L-level and one of signals /UW and /LW attains the L-level, the output signal of NOR gate 241 attains the L-level. In this case, the output signal of NAND gate 242 attains the H-level. In this state, therefore, the output signal of inverter 233 attains the H-level when signal /CAS lowers from the H-level to the L-level.
In this case, therefore, the output signal of NAND gate 234 lowers from the H-level to the L-level, and early write detecting signal EW rises from the L-level to the H-level in response to this lowering. The early write mode is set when signal EW attains the H-level as described above.
FIG. 15 is a circuit diagram of conventional lower and upper output buffers 600 and 700 for executing the early write mode.
Referring to FIG. 15, lower and upper buffers 600 and 700 correspond to those shown in FIG. 13. Upper output buffer 600 includes inverters 601-603, 62, 64 and 66, a 4-input NAND gate 606, 2-input NAND gates 63 and 65, and N-channel MOS transistors 67 and 68.
Upper output buffer 700 includes a 4-input NAND gate 607, inverters 72, 74 and 76, 2-input NAND gates 73 and 75, and N-channel MOS transistors 77 and 78. An inverter 608 for inverting signal /CAS0 may be included in any one of lower and upper output buffers 600 and 700.
In lower output buffer 600, signal /OE is applied to one of input terminals of NAND gate 606 through inverters 601-603. NAND gate 606 also receives on corresponding input terminals a signal DOTE, signal /CAS0 applied through inverter 608 and inverted signal /EW of signal EW. Signal DOTE indicates the fact that DRAM 103 is ready to start reading of data, and is supplied from clock generating circuit 20.
The output signal of NAND gate 606 is applied to one of input terminals of each of NAND gates 63 and 65 through inverter 62. The inverter 62 outputs a signal OEML indicative of the fact that lower output buffer 600 is reading data.
NAND gate 63 receives read data RDF output from sense-refresh amplifier and I/O control circuit 11 (see FIG. 13) on the other input terminal. NAND gate 65 receives read data /RDF at the inverted level of read data RDF on the other input terminal.
A power supply node N1 receives the power supply potential Vcc. A ground node N2 receives ground potential vss. Transistors 67 and 68 are connected in series between power supply node N1 and ground node N2. A node between transistors 67 and 68 is connected to one of terminals of data I/O terminal group 81.
The output signal of NAND gate 63 is applied to a gate electrode of transistor 67 through inverter 64. The output signal of NAND gate 65 is applied to a gate electrode of transistor 68 via inverter 66.
The upper output buffer 700 has a structure similar to that of lower output buffer 600. In upper output buffer 700, NAND gate 607 receives the same signal as NAND gate 606 in lower output buffer 600.
The output signal of NAND gate 607 is applied to one of input terminals of each of NAND gates 73 and 75. The output signal of inverter 72 is output as a signal OEMH indicative of that fact that upper output buffer 700 is reading data.
NAND gate 73 receives read data RDF on the other input terminal. NAND gate 75 receives read data /RDF on the other input terminal. Transistors 77 and 78 are connected in series between power supply node N1 and ground node N2. A node between transistors 77 and 78 is connected to one terminal in upper data I/O terminal group 82.
The output signal of NAND gate 73 is applied to a gate electrode of transistor 77 through inverter 74. The output signal of NAND gate 75 is applied to a gate electrode of transistor 78 through inverter 76.
Lower and upper output buffers 600 and 700 thus constructed operate as described below. Since these output buffers have the same structure, only lower output buffer 600 will be described below.
When both signals /EW and DOTE are at the H-level, and both signals /CAS and /OE are at the L-level, all the input signals in NAND gate 600 are at the H-level. Therefore, the output signal of NAND gate 600 is at the L-level.
In this state, DRAM 103 is ready to start reading of internal data, the early write mode is not detected, and both signals /CAS and /OE are at the L-level. In this case, signal OEML is at the H-level, and, in response to this, read data RDF is transmitted to data I/O terminal group 81.
During this transmission, if read data RDF is at the H-level, transistor 67 is on and transistor 68 is off, whereby data at the H-level is externally output. Meanwhile, if read data RDF is at the L-level, transistor 67 is off, and transistor 68 is on, so that data at the L-level is externally output.
When signal /EW among the signals sent to NAND gate 606 is at the L-level, that is; when the early write mode is detected, the output signal of NAND gate 606 is at the H-level. In this case, signal OEML is at the L-level, and read data RDF is not transmitted to data I/O terminal group 81. In this case, both transistors 67 and 68 are off, so that data sent from lower data I/O terminal group 81 is in the high-impedance state.
FIG. 16 is a circuit diagram of a conventional write control circuit for executing the early write mode.
Referring to FIG. 16, write control circuit 3 corresponds to that shown in FIG. 13. Write control circuit 3 includes NOR gates 331, 333, 335 and 346, inverters 332, 334, 336, 337, 339, 340, 343-345, 347, 348, 350 and 351, NAND gates 338, 342 and 349, and N-channel MOS transistors 341 and 352.
NOR gate 331 receives signal OEML on one of its input terminals, and receives signal OEMH on the other input terminal. The output signal of NOR gate 331 is output as a signal OOEMD for internally controlling the output of DRAM 103, and is also applied to one of input terminals of NOR gate 333. Signal /RASC is applied to the other input terminal of NOR gate 333.
The output signal of NOR gate 333 is applied to one of input terminals of NOR gate 335 through inverter 334, and is also applied to one of input terminals of NOR gate 346 through inverter 345. Signal /LW is applied to the other input terminal of NOR gate 335. Signal /UW is applied to the other input terminal of NOR gate 346.
The output signal of NOR gate 335 is applied to one of input terminals of NAND gate 338 via inverters 336 and 337. The output signal of NOR gate 335 is also applied to one of input terminals of NAND gate 342 through inverter 336.
Transistor 341 is connected between ground node N2 and a node formed between the output terminal of NOR gate 335 and the input terminal of inverter 336. Transistor 341 receives on its gate electrode the output signal of inverter 336.
The output signal of NOR gate 346 is applied to one of input terminals of NAND gate 349 through inverters 347 and 348. The output signal of NOR gate 346 is also applied to the other input terminal of NAND gate 342 through inverter 347.
Transistor 352 is connected between ground node N2 and a node formed between the output terminal of NOR gate 346 and the input terminal of inverter 347. Transistor 352 receives on its gate electrode the output signal of inverter 347.
The output signal of NAND gate 342 is applied to the other input terminal of each of NAND gates 338 and 349 through inverters 343 and 344. The output signal of NAND gate 338 is output through inverters 339 and 340 as a lower write enable signal /WEL. The output signal of NAND gate 349 is output through inverters 350 and 351 as an upper write enable signal /WEU.
Lower write enable signal /WEL is applied to write input buffer 4 (see FIG. 13), and upper write enable signal /WEU is applied to upper input buffer 5 (see FIG. 13). Each of these write enable signals /WEL and /WEU is operable to control the corresponding output buffer to attain the state for the write operation, when it attains the L-level.
The write control circuit 3 operates in the following manner. When at least one of lower and upper output buffers 600 and 700 is performing the read operation, and hence at least one of signals OEML and OEMH is at the H-level, or when signal /RAS is at the H-level indicative of the standby state, and hence signal /RASC is at the H-level indicative of the standby state, the output signal of NOR gate 333 is at the L-level.
In this case, one of the input signals of each of NOR gates 335 and 346 attains the H-level. Therefore, each of the output signals of NOR gates 335 and 346 attains the L-level.
In response to this, one of input signals of each of NAND gates 338 and 349 attains the L-level. Therefore, both signals /WEL and /WEU attain the H-level. In this case, therefore, the write operation using lower and upper input buffers 4 and 5 in FIG. 13 is not performed.
Meanwhile, when both signals OEML and OEMH are at the L-level owing to the fact that lower and upper output buffers 600 and 700 are not in the read operation state, and signal /RASC is at the L-level owing to the fact that signal /RAS is at the L-level, the output signal of NOR gate 333 is at the H-level.
In this case, one of the input signals of NOR gate 335 is at the L-level. Therefore, the output signal of NOR gate 335 attains the level equal to the inverted level of signal /LW. Likewise, one of the input signals of NOR gate 346 is at the L-level, so that the output signal of NOR gate 346 attains the level equal to the inverted level of signal /UW.
In this case, therefore, the output signal of one of the NOR gates corresponding to the one between signals /LW and /UW which attains the L-level attains the H-level. When the output signal of NOR gate 335 attains the H-level, both the two input signals of NAND gate 338 attain the H-level.
In this case, therefore, signal /WEL attains the L-level in response to the output signal at the L-level output from NAND gate 338. In this case, signal /WEU attains the H-level. Therefore, only lower input buffer 4 in FIG. 13 performs the write operation.
Meanwhile, when the output signal of NOR gate 346 attains the H-level, both the two input signals of NAND gate 349 attain the H-level. Therefore, the output signal of NAND gate 349 attains the L-level, and the signal /WEU attains the L-level in response to this. In this case, signal /WEL attain the H-level. Therefore, only upper input buffer 5 performs the write operation.
Now, description will be given on the operation in the early write mode of the DRAM shown in FIGS. 13 to 16. FIG. 17 is a timing chart showing the operation in the early write mode of DRAM 103 shown in FIGS. 13 to 16. Particularly, FIG. 17 shows the operation in the case that the early write mode is executed in accordance with a fast page mode byte control cycle.
In FIG. 17, there are shown signals /RAS and /CAS, address signals A0-A9, signals /UW and /LW, input data DQ1-DQ8 corresponding to lower input buffer 4, output data DQ1-DQ8 corresponding to lower output buffer 600, input data DQ9-DQ16 corresponding to upper input buffer 5, output data DQ9-DQ16 corresponding to upper output buffer 700 and signal /OE.
In the early write mode, as shown in FIG. 17, signal (e.g., signal /UW) is lowered from the H-level to the L-level after falling of signal /RAS for taking in a row address RA1 and before falling of signal /CAS for taking in a column address CA1. At this time, signal /LW is maintained at the H-level. In the case above, signal /LW may be lowered instead of signal /UW.
In response to these signals, early write detecting circuit 2000 shown in FIG. 14 detects the fact that the early write mode is designated. Thereby, signal EW output from early write detecting circuit 2000 attains the H-level. Thereafter, signal /CAS falls in accordance with a predetermined cycle for taking in column addresses CA2 and CA3.
In response to the H-level of signal /EW, lower and upper output buffers 600 and 700 shown in FIG. 15 set corresponding lower and upper output data DQ1-DQ8 and DQ9-DQ16 to high-impedance state HiZ, respectively.
In this case, both signals OEML and OEMH attain the L-level. Therefore, in response to the fact that signal /UW attains the L-level, signal /WEU output from write control circuit 3 shown in FIG. 16 attains the L-level.
Thereby, upper I/O terminal group 82 is used for writing data. Therefore, writing is performed by inputting effective data D1-D3 into upper input data DQ9-DQ16 corresponding to upper input buffer 5. Meanwhile, lower I/O terminal group 81 is not used for writing/reading data.
In DRAM 103 which can operate in the early write mode, one of lower and upper I/O terminal groups 81 and 82 can be used for the write operation while maintaining the other in the standby state.
In the conventional early write mode, however, only the write operation can be executed within one cycle of signal /RAS. In the prior art, however, such a read modified write mode has been used that the read operation and the write operation can be executed within one cycle of signal /RAS.
The read modified write mode will be described below. The following description will recite an example of executing the read modified write mode in DRAM 103 shown in FIG. 13.
FIG. 18 is a timing chart showing the operation in the read modified write mode of DRAM 103. In FIG. 18, signals shown therein are similar to those in FIG. 17, but I/O data DQ1-DQ16 each are shown as only upper or lower data or combination of upper and lower data.
Referring to FIGS. 13 and 18, signal /RAS is lowered to the L-level while signal /CAS is at the H-level. In response to this, clock generating circuit 20 applied a signal, which is used for internally taking in address signals A0-A9 as row address RA1 from address input terminal group 80, to address buffer 14.
Based on row address RA1 thus taken, row decoder 12 selects a word line in memory cell array 1. Thereby, data in the memory cells at the row corresponding to the selected word line is transmitted onto the bit line pair. Data transmitted onto the bit line pair is amplified by sense-refresh amplifier and I/O control circuit 11.
Then, signal /CAS is lowered to the L-level. During this, both signals /UW and /LW are at the H-level. In response to the change of signal /CAS, clock generating circuit 20 applied a signal, which is used for internally taking in address signals A0-A9 as column address CA1 from address input terminal group 80, to address buffer 14.
In this state, signals /UW and /LW are at the H-level. Therefore, lower and upper data I/O terminal groups 81 and 82 both operate in the read mode.
Thereby, based on the taken column address CA1, column decoder 13 transmits the data, which has been read onto the bit line pair as described before, to the lower and upper output buffers 600 and 700 through sense-refresh amplifier and I/O control circuit 11.
Then, signal/OE is lowered to the L-level. In response to this, data D1 is transmitted from lower and upper output buffers 600 and 700 to lower and upper data I/O terminal groups 81 and 82, respectively. The data thus transmitted is externally output.
Thereafter, signal /OE is raised to the H-level. Thereby, external output of data is completed. Subsequently, signal /UW (or /LW) is lowered to the L-level. By lowering only signal /UW to the L-level, upper input buffer 5 takes in upper data DQ9-DQ16 among data DQ1-DQ16 received by lower and upper I/O terminal groups 81 and 82.
Data thus taken is transmitted to the selected memory cells through sense-refresh amplifier and I/O control circuit 11, and is written into them.
According to the read modified write mode, the read operation and the write operation can be continuously executed for the selected memory cell within one cycle of signal /RAS. In the prior art, the operation in the read modified write mode must be controlled to use lower data I/O terminal group 81 for the read operation and use upper data I/O terminal group 82 for the write operation.
However, when executing the read operation and the write operation using the read modified write mode as described above, these operations cannot be performed simultaneously. Therefore, the read modified write mode is not suitable to data processing in which a fast access such as a fast page mode is performed.